#ifndef __SYSTEM_CLOCK_H__
#define __SYSTEM_CLOCK_H__

#include <rtthread.h>

/* ------------------------------------------------------------------------ *
 *  PLL Clocking Mode                                                       *
 * ------------------------------------------------------------------------ */
#define CLKIN                   1
#define OSCIN                   0

/* ------------------------------------------------------------------------ *
 *  PLL Divide By                                                           *
 * ------------------------------------------------------------------------ */
#define DIV_1                   0
#define DIV_2                   1
#define DIV_3                   2
#define DIV_4                   3
#define DIV_5                   4
#define DIV_6                   5
#define DIV_7                   6
#define DIV_8                   7
#define DIV_9                   8
#define DIV_10                  9
#define DIV_11                  10
#define DIV_12                  11
#define DIV_13                  12
#define DIV_14                  13
#define DIV_15                  14
#define DIV_16                  15
#define DIV_17                  16
#define DIV_18                  17
#define DIV_19                  18
#define DIV_20                  19
#define DIV_21                  20
#define DIV_22                  21
#define DIV_23                  22
#define DIV_24                  23
#define DIV_25                  24
#define DIV_26                  25
#define DIV_27                  26
#define DIV_28                  27
#define DIV_29                  28
#define DIV_30                  29
#define DIV_31                  30
#define DIV_32                  31

/* ------------------------------------------------------------------------ *
 *  PLL1 Controller                                                         *
 * ------------------------------------------------------------------------ */
#define PLL1_BASE               0x01c40800
#define PLL1_PID                *( volatile rt_uint32_t* )( PLL1_BASE + 0x0 )
#define PLL1_RSTYPE             *( volatile rt_uint32_t* )( PLL1_BASE + 0xe4 )
#define PLL1_PLLCTL             *( volatile rt_uint32_t* )( PLL1_BASE + 0x100 )
#define PLL1_PLLSECCTL             *( volatile rt_uint32_t* )( PLL1_BASE + 0x108 )
#define PLL1_PLLM               *( volatile rt_uint32_t* )( PLL1_BASE + 0x110 )
#define PLL1_PREDIV				*( volatile rt_uint32_t* )( PLL1_BASE + 0x114 )	
#define PLL1_PLLDIV1            *( volatile rt_uint32_t* )( PLL1_BASE + 0x118 )
#define PLL1_PLLDIV2            *( volatile rt_uint32_t* )( PLL1_BASE + 0x11c )
#define PLL1_PLLDIV3            *( volatile rt_uint32_t* )( PLL1_BASE + 0x120 )
#define PLL1_POSTDIV            *( volatile rt_uint32_t* )( PLL1_BASE + 0x128 )
#define PLL1_BPDIV              *( volatile rt_uint32_t* )( PLL1_BASE + 0x12c )
#define PLL1_PLLCMD             *( volatile rt_uint32_t* )( PLL1_BASE + 0x138 )
#define PLL1_PLLSTAT            *( volatile rt_uint32_t* )( PLL1_BASE + 0x13c )
#define PLL1_ALNCTL             *( volatile rt_uint32_t* )( PLL1_BASE + 0x140 )
#define PLL1_DCHANGE            *( volatile rt_uint32_t* )( PLL1_BASE + 0x144 )
#define PLL1_CKEN               *( volatile rt_uint32_t* )( PLL1_BASE + 0x148 )
#define PLL1_CKSTAT             *( volatile rt_uint32_t* )( PLL1_BASE + 0x14c )
#define PLL1_SYSTAT             *( volatile rt_uint32_t* )( PLL1_BASE + 0x150 )
#define PLL1_PLLDIV4            *( volatile rt_uint32_t* )( PLL1_BASE + 0x160 )
#define PLL1_PLLDIV5            *( volatile rt_uint32_t* )( PLL1_BASE + 0x164 )
#define PLL1_PLLDIV6            *( volatile rt_uint32_t* )( PLL1_BASE + 0x168 )
#define PLL1_PLLDIV7            *( volatile rt_uint32_t* )( PLL1_BASE + 0x16c )
#define PLL1_PLLDIV8            *( volatile rt_uint32_t* )( PLL1_BASE + 0x170 )
#define PLL1_PLLDIV9            *( volatile rt_uint32_t* )( PLL1_BASE + 0x174 )

/* ------------------------------------------------------------------------ *
 *  PLL2 Controller                                                         *
 * ------------------------------------------------------------------------ */
#define PLL2_BASE               0x01c40c00
#define PLL2_PID                *( volatile rt_uint32_t* )( PLL2_BASE + 0x0 )
#define PLL2_PLLCTL             *( volatile rt_uint32_t* )( PLL2_BASE + 0x100 )
#define PLL2_PLLM               *( volatile rt_uint32_t* )( PLL2_BASE + 0x110 )
#define PLL2_PREDIV				*( volatile rt_uint32_t* )( PLL2_BASE + 0x114 )	
#define PLL2_PLLDIV1            *( volatile rt_uint32_t* )( PLL2_BASE + 0x118 )
#define PLL2_PLLDIV2            *( volatile rt_uint32_t* )( PLL2_BASE + 0x11c )
#define PLL2_POSTDIV            *( volatile rt_uint32_t* )( PLL2_BASE + 0x128 )
#define PLL2_PLLCMD             *( volatile rt_uint32_t* )( PLL2_BASE + 0x138 )
#define PLL2_PLLSTAT            *( volatile rt_uint32_t* )( PLL2_BASE + 0x13c )
#define PLL2_ALNCTL             *( volatile rt_uint32_t* )( PLL2_BASE + 0x140 )
#define PLL2_DCHANGE            *( volatile rt_uint32_t* )( PLL2_BASE + 0x144 )
#define PLL2_CKEN               *( volatile rt_uint32_t* )( PLL2_BASE + 0x148 )
#define PLL2_CKSTAT             *( volatile rt_uint32_t* )( PLL2_BASE + 0x14c )
#define PLL2_SYSTAT             *( volatile rt_uint32_t* )( PLL2_BASE + 0x150 )

enum
{
	SYSCLK1,
	SYSCLK2,
	SYSCLK3,
	SYSCLK4,
	SYSCLK5,
	SYSCLK6,
	SYSCLK8,
};

//#define CLK_IN 27000000 //LVS301
#define CLK_IN 24000000   //LW332

void rt_hw_clock_init(void);

rt_uint32_t davinci_arm_clk_get(void);
rt_uint32_t davinci_timer0_clk_get(void);
rt_uint32_t davinci_emac_get(void);

#endif
